The present invention relates to a semiconductor memory device, and more particularly to an address counting block for a refresh mode of the semiconductor memory device.
A dynamic random access memory (DRAM) periodically performs a refresh operation to retain data. The refresh operation may be classified into an auto-refresh operation and a self-refresh operation. The auto-refresh operation and the self-refresh operation are identical to each other in that an address is internally generated, without any external application, but they are different from each other in view of refresh interval and period, application of an external command, and so on. The auto-refresh operation is rapidly performed because an auto-refresh command AREF is externally applied at a short period of, for example, a few tens ns. On the other hand, the self-refresh operation is relatively slowly performed because commands (SREF, SREX) indicating the beginning and end of the self-refresh are applied at a relatively long period of, for example, a few μs.
FIG. 1 is a block diagram of a conventional semiconductor memory device with an address counting block for a refresh mode.
Referring to FIG. 1, the conventional semiconductor memory device includes an internal address generator 10, a driving controller 20, and a core region 30. The internal address generator 10 generates a plurality of word line driving information signals MWLB<0:63> and a plurality of address information signals AX01<0:3>, AX<20>, AX<21> and MSB<0:7>, which are sequentially activated in response to a driving signal EN_RAB12 and a refresh signal REF. The driving controller 20 receives the plurality of address information signals AX01<0:3>, AX<20>, AX<21> and MSB<0:7> to generate a bit line driving signal BISHLB and word line driving information signals FXB<0:7>. The core region 30 accesses a corresponding cell in response to the bit line driving signal BISHLB and the word line driving information signals FXB<0:7>.
The internal address generator 10 includes an address counting unit 12 and a decoding unit 14. The address counting unit 12 counts internal addresses RAB<0:11> in sequence 1 bit by 1 bit in response to the driving signal EN_RAB12 and the refresh signal REF. The decoding unit 14 decodes the internal addresses RAB<0:11> to generate the plurality of word line driving information signals MWLB<0:63> and the plurality of address information signals AX01<0:3>, AX<20>, AX<21> and MSB<0:7>.
FIG. 2 is a circuit diagram of the address counting unit 12 illustrated in FIG. 1.
Referring to FIG. 2, the address counting unit 12 includes eleven 1-bit unit counters and a 1-bit unit counter, which are connected in series. The eleven 1-bit unit counters are configured to be activated in response to the refresh signal REF, and the 1-bit unit counter is configured to be activated in response to the driving signal EN_RAB12 and the refresh signal REF.
The internal addresses change in order from RAB<3> to RAB<8>, from RAB<0> to RAB<2>, and from RAB<9> to RAB<11> according to the application of the refresh signal REF and the driving voltage EN_RAB12. The order of the internal addresses RAB<0:11> may be changed according to the arrangement of the unit counters.
The semiconductor memory device uses internal addresses in the refresh operation, instead of external addresses. In other words, the refresh operation is performed using the internal (row) addresses RAB<0:11>, which are generated by the address counting unit 12 and increased 1 bit by 1 bit. The internal (row) addresses RAB<0:11> have a constant pattern during the refresh operation and thus the DRAM can estimate them. For reference, since external addresses inputted together with an active command have a random characteristic, the DRAM cannot estimate them.
FIG. 3 is a timing diagram illustrating the operation of the conventional semiconductor memory device of FIGS. 1 and 2.
Referring to FIG. 3, the refresh signal REF is activated whenever the auto-refresh command AREF is inputted. The address counting unit 12 is enabled in response to the driving signal EN_RAB12 and the refresh signal REF and increases the internal addresses RAB<0:11> 1 bit by 1 bit.
The decoding unit 14 decodes upper three bits RAB<9:11> of the internal addresses to generate the plurality of address information signals MSB<0:7>, decodes next six bits RAB<3:8> to generate the plurality of word line driving information signals MWLB<0:63>, and decodes the remaining 3 bits RAB<0:2> to generate the plurality of address information signals AX01<0:3>, AX<20> and AX<21>.
The driving controller 20 receives the plurality of address information signals AX01<0:3>, AX<20>, AX<21> and MSB<0:7> to generate the bit line driving signal BISHLB and the word line driving information signals FXB<0:7>.
The core region 30 selects cells corresponding to the word line driving information signals MWLB<0:63> and FXB<0:7> and transfers data of the selected cells in response to the bit line driving signal BISHLB.
In this way, the internal addresses RAB<0:11> are counted and increased 1 bit by 1 bit in response to the activation and precharge of the banks during the auto-refresh operation. Further, the internal addresses RAB<0:11> are decoded, and the word line driving information signals MWLB<0:63> and FXB<0:7>L and the bit line driving signal BISHLB are toggled. The toggling of each signal is generated only one time in order to apply the corresponding signal by decoding the internal addresses RAB<0:11> generated by the activation of the bank. All the signals are toggled to logic high level to initialize the addresses in the precharge operation.
When the auto-refresh command AREF is inputted, the memory is accessed by increasing the internal addresses RAB<0:11> 1 bit by 1 bit. As the internal addresses increase, the word line driving information signals change in order of MWLB<0>→MWLB<1>→MWLB<2>→MWLB<3>→ . . . →MWLB<63>, and then the word line driving information signals change in order of FXB<0>→FXB<1>→FXB<2>→FXB<3>→FXB<4>→FXB<5>→FXB<6>→FXB<7>. Then, the bit line driving signals change in order of BISHLB<0>→BISHLB<1>→BISHLB<2>→BISHLB<3>→BISHLB<4>→BISHLB<5>→BISHLB<6>→BISHLB<7>.
As illustrated in FIG. 3, the bits RAB<2:0> of the internal addresses do not change even though the fourth auto-refresh command AREF is inputted and thus the internal addresses RAB<0:11> are counted. Therefore, it can be seen that the word line driving information signal FXB<0> generated by decoding the bits RAB<2:0> of the internal addresses maintains a logic low level. Further, since the internal addresses RAB<11:9> does not change during the counting operation, the bit line driving signal BISHLB<0> generated by the internal addresses RAB<11:9> maintain a constant level. On the other hand, the levels of the internal addresses RAB<3:8> change as the address counting unit 12 is driven. Therefore, the word line driving information signals generated by decoding the internal addresses RAB<3:8> change in order of MWLB<0>→MWLB<1>→MWLB<2>→MWLB<3> . . . .
Although the levels of the word line driving information signal FXB<0> and the bit line driving signal BISHLB<0> do not change during a specific auto-refresh operation, the word line driving information signal FXB<0> and the bit line driving signal BISHLB<0> are toggled in every activation timing and precharge timing. This is because the decoding and resetting of the internal addresses RAB<0:11> are repeated in every activation and precharge.
Thus, a current is unnecessarily consumed by the toggling, although the word line driving information signal FXB<0> and the bit line driving signal BISHLB<0> have the constant levels during the refresh operation.
Meanwhile, to reduce the unnecessary current consumption caused by the toggling during the self-refresh mode, the semiconductor memory device prevents the toggling of the signal when the logic level of the corresponding signal does not change. For example, if unnecessary, the semiconductor memory device prevents the toggling of the word line driving information signals FXB<0:7> or the bit line driving signal BISHLB. If necessary, the semiconductor memory device allows the toggling, for example, when the internal addresses RAB<0:2> or the internal addresses RAB<9:11> are toggled. That is, the semiconductor memory device prevents or allows the toggling, depending on whether the internal addresses RAB<0:11> change or not.
However, the above operation in the self-refresh mode cannot be applied during the auto-refresh mode. This is because the beginning and end of the self-refresh mode are easy to be defined using the external command, but the beginning and end of the auto-refresh mode are difficult to be defined because there is no specific external command indicating them.